1. Field of the Invention
The present invention relates to classifying failing semiconductor memories, and more particularly to a method of classifying memories based on pass/fail information.
2. Discussion of the Prior Art
The process of manufacturing semiconductor memories is one of the drivers of higher integration technologies. Testing memories gives feed back for the improvement of the manufacturing process. During testing, bit fail maps are generated showing failed memory cells. Bit maps are used to determine a repair solution to replace failed memory cells with good spare ones and/or determine an improved manufacturing process. Due to the regularity of the memory array fail patterns can be related to process problems.
During a typical test flow for semiconductor memories low temperature and high temperature burn-in tests are done after assembly. Burn-in is the process of stressing a memory device to expose faulty memory cells, e.g., to make faulty memory cells fail. During burn-in a small number of new fails are induced and detected. An example of a pareto chart is shown in FIG. 1. Low and high temperature testing finds any remaining temperature and speed specific fails. To improve yields these fails can be analyzed to determine the process root cause. A bit fail map gives the fail location and fail type to perform successful physical failure analysis at the failed site. Due to cost constraints and high parallelism in the burn-in oven (tester) and high-speed memory tests, no known bit fail map capability is currently available on component production testers. Therefore, extra engineering equipment is used for analysis. This improves cost but limits the analysis to a small sample site. According to Table 1, testers at different test stages are compared for parallelism, speed and catch RAM size requirements for analysis.
TABLE 1Wafer TestBurn-inComponent TestParallelism16–6410,00016–256Cycle Time16–32 ns40–200 ns2.5–10 nsClock Speed62–34 MHz25–5 MHz400–100 MHzCatch RAM32 ns RMW cycle, 256 Mbit deviceSize2*256*64 Mbit =256*10 k Mbit =16*256*256 Mbit =32 Gbit2.5 Tbit1 TbitThe wafer test shown in Table 1 has low parallelism and low speed and needs less capture memory for full bit maps. Burn-in tests stress a high number of memory devices and therefore would need a larger catch RAM than a wafer test. Component tests run at high-speed and need cheap slow memory in parallel to catch all fails. The catch RAM size adds a substantially to the cost of the test and is therefore often omitted in the manufacturing environment.
Memory testing systems detect memory faults caused by, inter alia, faulty processing, faulty interconnects, timing related failures, etc. According to existing testing techniques for a memory device under test (DUT), a catch-RAM or a vector memory is needed to store the address of each failing bit. Current memory devices can be over sixteen megabytes in size, additionally, memory devices are often tested in parallel to increase the efficiency of the testing, resulting in an increased need for DUT memory. The size of the DUT memory corresponds to the capacity and number of memory devices being tested. Current DUT memory capacities can exceed four Gigabytes.
Current memory sizes may be too large to economically store all fail information. Fail capture systems can test each pin on a memory device. The memory device may be, for example, dynamic random access memory (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), and Double Data Rate-SDRAM (DDR SDRAM), as well as non-volatile (NV) memory devices such as NV RAM. These memory devices may be part of a memory module, such as, single in-line memory module (SIMM), or dual in-line memory module (DIMM). However, as these memories become larger, the need for DUT memory increases, increasing the expense of the testing system.
Therefore, a need exists for a system and method of classifying faulty memories based on pass/fail information for a portion of an address space.